Analog phase locked loop (PLL) circuits are well known in the art. Such circuits typically include a charge pump, a loop filter and a ring oscillator. The bandwidth of the PLL circuit is dependent on the charge pump current, the resistance in the loop filter and the gain of the voltage controlled oscillator (VCO) which is generally referred to as KVCO gain. In many implementations the changes in current and resistance compensate each other, and so the spread of the PLL circuit bandwidth is primarily determined by the variation in KVCO gain.
Change in the bandwidth of the PLL circuit produces a corresponding change in integrated jitter values which adversely affect the cut-off frequency of the PLL circuit high pass filter function that shapes VCO noise. It is therefore important to keep the PLL bandwidth constant with process, voltage and temperature variation (referred to PVT variation) in order to achieve satisfactory integrated jitter numbers, improve PLL circuit stability and better control lock time of the PLL circuit. This design goal must be accomplished with minimal impact on VCO phase noise. For example, an increase in phase noise can be better shaped with a constant bandwidth PLL circuit.
There is accordingly a need in the art for a compensated PLL circuit exhibiting a stable bandwidth over a range of temperature variation.